As a liquid crystal display device for displaying a still image, there has been a liquid crystal display device which includes a pixel memory for displaying an image by (i) provisionally retaining image data written in a pixel, and (ii) carrying out a refresh operation while reversing a polarity of the image data. In a normal operation for displaying a multiple gray-scale moving image, new image data is written in the pixel via a data signal line every frame. Meanwhile, in a memory operation for displaying a still image, image data retained in the pixel memory is used. For this reason, during a time period in which the refresh operation is carried out, it is unnecessary to supply, to the data signal line, new image data to be written.
Accordingly, an operation of a circuit for driving a scan signal line and an operation of a circuit for driving the data signal line can be stopped during the time period of the memory operation. This makes it possible to reduce power consumption. Moreover, the power consumption can be further reduced since (i) the number of times that the data signal line, having a large capacity, is charged and discharged, can be reduced, and (ii) it is unnecessary to transfer, to a controller, image data corresponding to the time period of the memory operation.
For the reasons described above, a pixel for carrying out such a memory operation is often employed for a case where a low-power consumption property is strongly required, such as a case where a standby screen is displayed on a mobile phone.
FIG. 38 is a view illustrating only a memory circuit part in each pixel structure of a liquid crystal display device employing such a pixel memory. The pixel structure illustrated in FIG. 38 has a liquid crystal capacitor C1c (indicated by a dotted line) so that the pixel having the pixel structure can be used as a pixel for a liquid crystal display device. Such a pixel structure is identical with a structure disclosed in Patent Literature 1, for example.
A memory circuit MR100 serving as the memory circuit part includes a switching circuit SW100, a first data retention section DS101, a data transfer section TS100, a second data retention section DS102, and a refresh output control section RS100.
The switching circuit SW100 is constituted by a transistor N100, which is an N-channel TFT. The first data retention section DS101 is constituted by a capacitor Ca100. The data transfer section TS100 is constituted by a transistor N101, which is an N-channel TFT. The second data retention section DS102 is constituted by a capacitor Cb100. The refresh output control section RS100 is constituted by an inverter INV100 and a transistor N103, which is an N-channel TFT. The inverter INV100 is constituted by a transistor P100, which is a P-channel TFT, and a transistor N102, which is an N-channel TFT.
Further, for each of rows of a pixel matrix, the following lines are provided to drive each memory circuit MR100: a data transfer control line DT100; a switch control line SC100; a high power source line PH100; a low power source line PL100; a refresh output control line RC100; and a capacitor line CL100. Furthermore, for each of columns of the pixel matrix, a data input line IN100 is provided.
As to a field-effect transistor such as the aforementioned TFTs, one of a drain terminal and a source terminal is referred to as “first drain/source terminal”, and the other one of the drain terminal and the source terminal is referred to as “second drain/source terminal”. Note, however, that, in a case where which one of the first and second drain/source terminals serves as the drain terminal and which one of the first and second drain/source terminals serves as the source terminal are determined on the basis of a direction in which a current flows between the first and second drain/source terminals, the first and second drain/source terminals are merely referred to as “drain terminal” and “source terminal”, appropriately. A gate terminal of the transistor N100 is connected to the switch control line SC100. A first drain/source terminal of the transistor N100 is connected to the data input line IN100. A second drain/source terminal of the transistor N100 is connected to a node PIX which is connected to one of ends of the capacitor Ca100. The other one of ends of the capacitor Ca100 is connected to the capacitor line CL100.
A gate terminal of the transistor N101 is connected to the data transistor control line DT100. A first drain/source terminal of the transistor N101 is connected to the node PIX. A second drain/source terminal of the transistor N101 is connected to a node MRY which is connected to one of ends of the capacitor Cb100. The other one of ends of the capacitor Cb100 is connected to the capacitor line CL100.
An input terminal IP of the inverter INV100 is connected to the node MRY. A gate terminal of the transistor P100 is connected to the input terminal IP of the inverter INV100. A source terminal of the transistor P100 is connected to the high power source line PH100. A drain terminal of the transistor P100 is connected to an output terminal OP of the inverter INV100. A gate terminal of the transistor N102 is connected to the input terminal IP of the inverter INV100. A drain terminal of the transistor N102 is connected to the output terminal OP of the inverter INV100. A source terminal of the transistor N102 is connected to the low power source line PL100. A gate terminal of the transistor N103 is connected to the refresh output control line RC100. A first drain/source terminal of the transistor N103 is connected to the output terminal OP of the inverter INV100. A second drain/source terminal of the transistor N103 is connected to the node PIX.
Note that, in a case where a pixel is constituted in such a manner that the memory circuit MR100 includes the liquid crystal capacitor C1c, the liquid crystal capacitor C1c is connected between the node PIX and a common electrode COM.
Next, the following description deals with an operation of the memory circuit MR100 with reference to FIG. 39.
FIG. 39 shows a case where the memory circuit MR100 is in a memory operation mode, e.g., in displaying a standby screen of a mobile phone etc. Further, to the data transfer control line DT100, the switch control line SC100, and the refresh output control line RC100, a binary-level (represented by a high (active) level or a low (inactive) level) potential is applied from a driving circuit (not illustrated). The high level and the low level of the binary level voltage can be set for each of the lines described above, independently. To the data input line IN100, a binary logical level represented by a high level or a low level is supplied from another driving circuit (not illustrated). A potential supplied via the high power source line PH100 is identical with the high level of the binary logical level, while a potential supplied via the low power source line PL100 is identical with the low level of the binary logical level. Further, a potential supplied via the capacitor line CL100 can be either (i) constant or (ii) variable at predetermined timing. Here, the potential supplied via the capacitor line CL100 is constant for the sake of simple explanation.
The memory operation mode has a writing time period T101 and a refreshing time period T102. During the writing time period T101, data to be retained by the memory circuit MR100 is written. The writing time period T101 is constituted by a time period t101 and a time period t102 which sequentially follows the time period t101. During the writing time period T101, writing is carried out with respect to the memory circuits MR100, row by row, sequentially. For this reason, the time period t101 is set for each of the rows so as to terminate within a time period in which corresponding writing data is outputted. Further, as timing when the time period t102 terminates, the same timing is set for all of the rows, that is, as timing when the writing time period T101 terminates, the same timing is set for all of the rows. During the refreshing time period T102, the data, which has been written in the memory circuit MR100 during the writing time period T101, is retained while being refreshed. For all of the rows, the refreshing time period T102 is started simultaneously. The refreshing time period T102 is constituted by continuous time periods t103 through t110, which are sequentially provided.
During the time period t101 of the writing time period T101, the potential of the switch control line SC100 is high, while the potentials of the data transfer control line DT100 and the refresh output control line RC100 are low. This turns on the transistor N100, so that a potential of data (here, the potential is high), supplied to the data input line IN100, is written in the node PIX. During the time period t102, the potential of the switch control line SC100 becomes low. This turns off the transistor N100, so that an electric charge corresponding to the potential of data thus written is retained by the capacitor Ca100.
Here, in a case where the memory circuit MR100 is constituted by only the capacitor Ca100 and the transistor N100, the node PIX is in a floating state during a time period in which the transistor N100 is in an OFF state. In this case, ideally, the electric charge is retained by the capacitor Ca100 so that the potential of the node PIX is maintained to be high. In an actual situation, however, an off-leakage current is generated in the transistor N100. Accordingly, the electric charge retained by the capacitor Ca100 is gradually leaked to the outside of the memory circuit MR100. As the electric charge retained by the capacitor Ca100 is leaked, the potential of the node PIX is changed. In a case where the electric charge is leaked for a long time, the potential of the node PIX is changed to such a degree that the potential of data thus written loses its original meaning.
In view of this, the data transfer section TS100, the second data retention section DS102, and the refresh output control section RS100 are caused to refresh the potential of the node PIX so that the data which has been written would not be lost.
In order not to lose the data thus written, the writing time period T101 is followed by the refreshing time period T102. During the time period t103, the potential of the data transfer control line DT100 becomes high. This turns on the transistor N101, so that the capacitor Ca100 and the capacitor Cb100 are electrically connected in parallel to each other via the transistor N101. The capacitor Ca100 is set to have a greater capacitance than that of the capacitor Cb100. Accordingly, an electric charge is transferred between the capacitors Ca100 and Cb100, so that the potential of the node MRY becomes high. From the capacitor Ca100 to the capacitor Cb100, a positive electric charge is transferred via the transistor N101, until the potential of the node PIX becomes identical with that of the node MRY. This reduces the potential of the node PIX by a small voltage ΔV1, as compared with the potential of the node PIX during the time period t102. However, the potential of the node PIX is still in a range of the high level. During the time period t104, the potential of the data transfer control line DT100 becomes low. This turns off the transistor N101. As a result, (i) the electric charge is retained by the capacitor Ca 100 so that the potential of the node PIX is maintained to be high and (ii) the electric charge is retained by the capacitor Cb100 so that the potential of the node MRY is maintained to be high.
During the time period t105, the potential of the refresh output control line RC100 becomes high. This turns on the transistor N103, so that the output terminal OP of the inverter INV100 is electrically connected to the node PIX. Since a reversal potential (here, the reversal potential is low) with respect to the potential of the node MRY is supplied to the output terminal OP, the node PIX is charged with the reversal potential. During the time period t106, the potential of the refresh output control line RC100 becomes low. This turns off the transistor N103. Accordingly, the electric charge is retained by the capacitor Ca100 so that the potential of the node PIX is maintained to be the reversal potential.
During the time period t107, the potential of the data transfer control line DT100 becomes high. This turns on the transistor N101, so that the capacitor Ca100 and the capacitor Cb100 are electrically connected in parallel to each other via the transistor N101. Accordingly, an electric charge is transferred between the capacitor Ca 100 and the capacitor Cb100, so that the potential of the node MRY becomes low. From the capacitor Cb100 to the capacitor Ca100, a positive electric charge is transferred via the transistor N101, until the potential of the node MRY becomes identical with the potential of the node PIX. This increases the potential of the node PIX by a small voltage ΔV2 as compared with the potential of the node PIX during the time period t106. However, the potential of the node PIX is still in a range of the low level.
During the time period t108, the potential of the data transfer control line DT100 becomes low. This turns off the transistor N101. As a result, (i) the electric charge is retained by the capacitor Ca 100 so that the potential of the node PIX is maintained to be low and (ii) the electric charge is retained by the capacitor Cb100 so that the potential of the node MRY is maintained to be low.
During the time period t109, the potential of the refresh output control line RC100 becomes high. This turns on the transistor N103, so that the output terminal OP of the inverter INV100 is electrically connected to the node PIX. Since the reversal potential (here, the reversal potential is high) with respect to the potential of the node MRY is supplied to the output terminal OP, the node PIX is charged with the reversal potential. During the time period t110, the potential of the refresh output control line RC100 becomes low. This turns off the transistor N103. Accordingly, the electric charge is retained by the capacitor Ca 100 so that the potential of the node PIX is maintained to be the reversal potential.
The operations of the time periods t103 through t110 are repeated until the refreshing time period T102 is followed by the next writing time period T101. The potential of the node PIX is refreshed to the reversal potential during the time period t105, and is then, during the time period t109, refreshed to the potential supplied at the time of the writing. Note that, in a case where a low potential of data is written in the node PIX during the time period t101 of the writing time period T101, a waveform of the potential of the node PIX is such that a waveform of the potential, shown in FIG. 39, is reversed.
As described above, according to the memory circuit MR100 employing such a data inversion method, the data thus written is retained while being refreshed. In a case where the memory circuit MR100 includes the liquid crystal capacitor C1c, the potential of the common electrode COM may be set so as to be reversed between the high level and the low level at timing when the data is refreshed. In this case, it is possible to refresh black display data or white display data while causing such data to be subjected to polarity reversal.